1. Field of the Invention
The present invention relates to a package structure and manufacturing method thereof; in particular, to a package structure and manufacturing method thereof about enhancing packaging spatial utilization.
2. Description of Related Art
At present, the electronic products have been common in fields of entertainment, communication, power conversion, internet, computers, and consumer products. The electronic products can also be found in military applications, aviation, automobiles, industrial controllers, and office equipments. The electronic products are emphasized on short, thin, and light, so that the density of distribution of electronic components and circuit is too high. Besides, there is an increase in demand for improving the system processing speed and reducing the sizes of the electronic components. The objective of fabricating electronic products is not only maintaining high efficiency and quality of stabilization but also enhancing spatial utilization.
The efficiency of the system is related to the structure of the system. At present, although Through Silicon Via (TSV) in wafer manufacturing process is emphasized on economizing space and wiring length by stacking die, the reducible wiring length is limited and at most is on the order of millimeter. When the development of electronic products tends to miniaturization, the objective of designing electronic products is to have a smaller and thinner packing structure.